1. Field of the Invention
The present invention relates generally to a computer-based simulation model for simulating the operation of an electrical circuit. More specifically, the invention relates to a method, apparatus, and system of employing an object-oriented programming convention for simulating hierarchical circuits.
2. Background of the Invention
During the manufacture and testing of electrical circuits, simulators are often constructed to simulate the operation or behavior of such circuits. These circuit simulations are used to detect flaws in a circuit's design and to check a component's interaction with other components in a larger circuit.
The term "simulator" as used herein broadly refers to a software program that simulates actions of electronic circuits by exercising interconnected simulation models. The term "simulation model" broadly refers to a software representation of a circuit component. It also should be noted that the term "circuit" as used herein broadly refers to a combination of electrical components that cooperate to perform a particular function. The type of circuit that may be simulated according to the present invention ranges from a simple on/off switch to a complex super computer.
Traditionally, circuits have been described using netlist languages which are well known in the art. A netlist language is characterized by a number of constructs. First, a netlist language defines input and output ports of a subcircuit. A port is a connection to a subcircuit. Second, a netlist language represents connections between ports. Third, it can represent a nested subcircuit within a circuit. And fourth, a netlist language has some measure of extension capability for tagging properties to ports, connections, and/or subcircuits.
Conventional netlist model languages used for simulating hierarchical circuits include, for example, EDIF netlist view (EDIF, Electronic Design Interchange Format, Standard 2.0, Electronic Industries Association, Washington, D.C., December, 1993); structural VHDL (IEEE Standard VHDL Language Reference Manual, Std 1076-1993, IEEE, New York, 1993); and VERILOG (IEEE Standard 1364-1995).
Although these model languages are suitable usually for traditional simulation applications, such as detecting faults in circuit designs, they tend to be inadequate for newer applications, such as debugging application code running on a simulated processor. Netlist language simulation models tend to be monolithic. A circuit modeler is limited to data formats and run-time signal propagation strategies hard coded into the simulation engines. Consequently, in non-traditional application, hand coding usually is required.
Hand coding is problematic for a variety of reasons. Among the more significant shortcomings is the high cost and time it requires. Rather than turning to a convenient library of precoded simulation modules, a modeler must examine a particular component to be simulated, and then develop a programming approach on an ad hoc basis. Such an investment of time tends to discourage the development of unique and highly specialized models.
Hand coding not only is time consuming and expensive, but also results in a lack of standardization which has several detrimental effects. For example, it results in disparate programming techniques and approaches. This necessarily means that some components will be more skillfully modeled than other components. Since all the simulation models must cooperate, however, one substandard model can compromise the entire simulation model.
Aside from a lack of standardization, the disparate programming techniques render simulation analysis or modification difficult. For example, to analyze a potential problem in the circuit, the modeler must first become acquainted with the modeling approach taken to simulate the behavior of a particular component. When models simulate circuit behavior in different ways, it also is difficult to determine readily where a problem lies. In other words, there is no systematic approach to debugging; there is no standardized "tap" to plug into to determine the step-wise propagation of a signal.
Therefore, a need exists for a simulation model that not only provides the familiarity of conventional netlist languages, but also runs efficiently without incurring the traditional netlist overhead and offers flexibility with extension capability. The present invention fulfills this need among others.